1. Field of the Invention
The present invention relates to the field of channel selecting circuits for television signal receivers and, in particular, to a frequency synthesis circuit for use in channel selecting circuits which synthesizes a selected channel frequency quickly and efficiently.
2. Description of the Related Art
In general, a particular television signal received by an antenna is selected by use of a tuner. The received signal is amplified and detected by a video intermediate frequency (IF) circuit. The output video signal is taken from the video IF circuit and a synchronous voltage is developed to control the selection of a particular broadcast signal. A known circuit for outputting the synchronous control voltage is described below.
A PLL (phase locked loop) frequency synthesizer system is adapted for use in a channel selecting circuit of a known color television receiver. The channel selecting circuit using the PLL frequency synthesizer system has a tuner and a PLL circuit which supplies synchronous voltage for controlling a local oscillator of the tuner.
The PLL circuit has a prescaler which divides the local oscillating signal supplied from the tuner, a reference oscillator which oscillates a highly accurate signal, a first divider which divides the signal supplied from the prescaler by N, a second divider which divides the signal supplied from the reference oscillator by X, and a phase comparator which compares the phases between the outputs of the first and second dividers. The output from the phase comparator is supplied to the local oscillator of the tuner as a synchronous voltage through a filter circuit for smoothing the phase comparator output.
To be precise, the dividing ratios of the prescaler and the second divider are 1/8 and 1/512, respectively. The frequency of the known reference oscillator is 4 MHz. The output frequency fr of the second divider is then 7.8125 kHz (=4 MHz/512). The dividing ratio of the first divider is varied by control of a microcomputer.
A user orders the microcomputer to receive the desired channel through an input unit, typically a remote control. In many instances, the users may select a very high frequency channel after having viewed a very low frequency channel. Known tuning systems are slow to respond to such orders. The microcomputer changes the dividing ratio of the first divider and also changes the locked frequency of the PLL circuit. A local oscillating frequency fosc in the tuner is as follows: EQU fosc=fr.8.N
The minimum interval of frequency change is 62.5 kHz (=7.8125 kHz.8).
Additionally, a television broadcast signal may really be offset to the broadcast standard. This offset is discussed later.
The operation of the channel selecting circuit is described below on the condition that the intermediate frequency fo' of the broadcast signal of the received channel is offset from the standard intermediate frequency fo of the channel.
Now, if the user selects another desired channel at the time t0, that is, if the dividing ratio N of the first divider is changed by control of the microcomputer, a phase difference occurs as a result of a comparison in the phase comparator. The correction of the synchronous voltage for cancelling the phase difference is carried out every time interval tx by the phase comparator. The time interval tx for the correction is 0.128 msec (=1/7.8125 kHz), because the output frequency fr of the second divider equals 7.8125 kHz. The synchronous voltage becomes stable after the corrections of the synchronous voltage are done. After the synchronous voltage becomes stable, next, the microcomputer operates a signal retrieval so that the intermediate frequency tunes in the selected one of the broadcast.
In this case, the minimum interval of frequency change is 62.5 kHz and the intermediate frequency may not converge to the broadcast signal quickly which is at a frequency interval of 62.5 kHz. If the minimum interval of frequency change is inadequate, dividing steps of the first and second dividers have to be increased, e.g. the dividing ratio of the second divider should equal 1/1024 (then, the output frequency fr of the second divider will be 3.90625 kHz). In this case, the minimum interval of frequency change becomes 31.25 kHz. However, as the minimum interval of frequency change is decreased, the time interval for correction of the synchronous voltage increases to 0.256 msec (=1/3.90625 kHz) and the response time becomes longer. That is, when the channel selected is changed, the time t1 until the synchronous voltage becomes stable is longer. When the microcomputer retrieves a real broadcasting signal so that the intermediate frequency f0 tunes in the real intermediate frequency f0' of the broadcasting signal, the response time until the tuning is completed increases too.